Electronic components include electronic devices, such as field programmable gate arrays (FPGAs) and application specific integrated circuits (ASICs), supported on a printed circuit board (PCB). These electronic devices are manufactured on semiconductor substrates by sequential processing steps. Multiple electronic devices can be manufactured on a single substrate. These multiple electronic devices on the single substrate are sliced into multiple dies (or chips) after the sequential processing steps are completed and all the devices are formed. Prior to being placed on the PCB, these electronic devices (or dies) are placed in packages to allow the devices to be handled and to be electrically coupled to the PCB. There are vias and interconnects (wires) in packages that provide an electrical network for the die to be electrically coupled to the PCB and to enable access to other devices. The packaged dies are then disposed on the PCB through metallic connections, such as a ball grid array (BGA).
PCB provides power source(s) and grounding path(s) for devices on the packaged die to enable the functions of the devices on the die. The electrical paths for the power source and for grounding in the package, between the PCB and the die, are also being called the power distribution network for the devices. Power distribution networks create loop inductance, due to the opposing directions and proximity of the power paths and grounding paths. Loop inductance of the power distribution network reduces the voltage supplied by the power source on the PCB to the electrical devices on the die, defining a voltage drop (ΔV). The voltage supplied by the power source is used to turn the devices on and off. In one embodiment, the voltage supplied by the PCB is DC voltage for devices such as FPGAs or ASICs. If the loop inductance is high, the voltage drop can be high enough to affect the on/off function the devices on the die.
The problem of loop inductance causing voltage drops is not so much of a concern when the operating voltage of the electronic device is at a relatively high voltage, such as 5.5 volts. Due to advancements in device technology, the operating voltage has steadily reduced from 5.5 volts to 3.3 volts, and to 1.8 volts, and lower. At low operating voltages, such as 1.8 volts, the voltage drop caused by the loop inductance can be high enough to affect the on/off function of the electrical devices (e.g. transistors) on the dies. The problem of loop inductance also becomes worse with increases in clock frequency, which decreases the amount of time a device is turned on or off (also called turn-on or turned-off time). When a device is turned on, the current through the device increases from zero to a current, Ion, within the turn-on time. Similarly, when a device is turned off, the current through the device decreases from Ion to zero.
Equation (1) below shows the relationship between ΔV to inductance (L). Voltage drop (ΔV) is about equal to inductance (L) multiplying dI/dt, which is current increase or decrease rate.ΔV=LdI/dt  (1)As described above, higher clock frequency pushes the dI/dt value higher. At the same time, lower operating voltage for advanced devices pushes the acceptable ΔV lower. Therefore, the loop inductance must be reduced for advanced device operation.
In addition to device functionality concerns, the chip areas available for vias for power distribution networks on packages of dies and manufacturing cost of the vias also must be considered during the design of the power distribution network.
Therefore, there is a need for a method for choosing via layout patterns that meet the limits of loop inductance, available chip areas, and manufacturing cost.